With the development of the semiconductor technology, integrated circuits with higher performance and more powerful functions require greater element density. Thus, the sizes of the components need to be scaled further.
However, with the continuous reduction of the sizes of the integrated circuit, the constant material properties and physical effects for the operation of the transistor and other elements are inevitably impaired. Accordingly, in order to maintain the performance of the components, many new innovations in the design of transistors have been worked out.
The carrier mobility is a critical factor to maintain the performance of field effect transistors. When an voltage is applied to the gate isolated from the channel by a very thin gate dielectric, there are some negative influences on the current or charge flowing in the channel of the doped semiconductor caused by the carrier mobility.
It is known that the mechanical stress in the channel region of the FET may, depending on the type of carriers and the direction of the stress, significantly increase or reduce the carrier mobility. In the FET with channels usually formed along 110 orientation, the tensile stress along the direction of the source/drain region may improve the mobility of electrons while reducing the mobility of holes, which may advantageously improve the performance of the NMOS. The compressive stress along the direction of the source/drain region may improve the mobility of holes while reducing the mobility of electrons, which may advantageously improve the performance of the PMOS. A large amount of structures and materials have already been proposed in the prior art to generate tensile stress or compressive stress in semiconductor materials. For example, US2006/0160317 has already proposed a solution for improving the carrier mobility in the channel by depositing a stress layer on a MOSFET device, and then selectively etching the entire or partial gate layer.
However, the carrier mobility is typically changed by the stress layer or stress interface in prior art, which is disadvantageous to continuously reduce the size of the device and may lead to a complicated manufacturing process. Moreover, with the reduction of the size of the semiconductor device currently, the corresponding channel region is decreased accordingly. As a result, for the stress material applied to the source and/or drain regions on both sides of the channel region, when the stress material expands, the corresponding increase of the stress is very limited, which may not advantageously improve the performance of the MOSFET transistor (e.g. on-off current ratio). As a result, the COMS circuit formed by the above-mentioned method has a poor performance. Therefore, it requires a new method for manufacturing the semiconductor device, which may advantageously improve the carrier mobility at the channel region of the NMOS and/or PMOS device, and at the same time reduce the size of the device and simplify the manufacturing process.